Information processing apparatuses typified by data processing apparatuses such as CPUs (central processing units), DSPs (digital signal processors) and filters, as well as buses and data paths for data exchanges perform various operations in synchronism with a synchronizing clock signal (system clock). One such information processing apparatus designed to carry out a process on a plurality of clock pulses include storage devices such as flip-flop circuits that store the results of halfway operations making up the process (e.g., refer to Japanese Patent Laid-open No. 2002-204224).
That type of processing is generally called pipeline processing. The above-mentioned flip-flop circuits or the like for storing halfway processing results constitute what is known as a pipeline. The layout of the pipeline is delimited by so-called segments.
Each of the segments making up the pipeline is generally located where operation status is low, or where the circuits upstream and downstream of the segment in question keep their transition times (i.e., a time period that elapses from the time data is input to the circuit in question until the input data is processed and output) shorter than the cycle of the synchronizing clock signal in use.
Conventionally, when the synchronizing clock signal has a variable frequency, the pipeline is most often constructed (i.e., segmented) to operate primarily in keeping with the highest frequency of the signal. If the frequency of the clock signal is reduced, the transition time of pipeline circuitry falls far short of the synchronizing clock cycle. As a result, with the pipeline designed to function best at the highest synchronizing clock frequency, lowered clock frequencies can appreciably reduce pipeline functionality.
In a related-art system architecture where the synchronizing clock signal is varied in frequency and where the pipeline is designed to operate in keeping with the highest clock frequency, drops in the clock frequency often lead the entire processing performance of the system to deteriorate while power is being consumed wastefully, as outlined above.
FIG. 1 is a block diagram of a related-art information processing apparatus 1 operating on a pipeline basis. As shown in FIG. 1, the information processing apparatus 1 comprises a frequency control block 11 and holding blocks 12-1 through 12-4. The frequency control block 11 varies the frequency of a synchronizing clock signal CLK based on predetermined frequency information Infq, and outputs the synchronizing clock signal CLK at the varied frequency. Each of the holding blocks 12-1 through 12-4 inputs and holds predetermined data on detecting a leading or a trailing edge of a given clock pulse in the synchronizing clock signal CLK from the frequency control block 11, and outputs the data held therein when detecting a leading or a trailing edge of the next clock pulse.
The information processing apparatus 1 also includes a signal processing block 13-1 located between the holding blocks 12-1 and 12-2, a signal processing block 13-2 between the holding blocks 12-2 and 12-3, and a signal processing block 13-3 between the holding blocks 12-3 and 12-4. The signal processing block 13-1 performs a first process on an input signal (i.e., data) and outputs the processed signal; the signal processing block 13-2 carries out a second process on the input signal (data) and outputs the processed signal; and the signal processing block 13-3 executes a third process on the input signal (data) and outputs the processed signal.
In other words, a pipeline is formed by the four holding blocks 12-1 through 12-4 in the information processing apparatus 1. The pipeline is segmented immediately upstream and downstream of each of the signal processing blocks 13-1 through 13-3.
How the information processing apparatus 1 works is described below with reference to FIGS. 2 and 3. Described first with reference to FIG. 2 is how the information processing apparatus 1 operates when the synchronizing clock signal CLK is set for its highest frequency.
In this example, a signal input to the information processing apparatus 1, i.e., a signal entered into the holding block 12-1, is illustratively a data string (A0, B0, C0, D0). The four data items constituting the data string (A0, B0, C0, D0) are input to the holding block 12-1 successively, one at a time per clock pulse.
On a first clock pulse, the data item A0 is input to and held by the holding block 12-1, as shown in FIG. 2.
On a second clock pulse, the holding block 12-1 inputs and holds the data item B0 while outputting the data item A0 concurrently. The data item A0 is converted into a data item Al after undergoing the first process performed by the signal processing block 13-1. The data item A1 is input to and held by the holding block 12-2 until a third clock pulse is output.
On the third clock pulse, the holding block 12-1 inputs and holds the data item C0 while outputting the data item B0 concurrently. The holding block 12-2 outputs the data item A1 while concurrently inputting a data item B1 derived by the signal processing block 13-1 from the data item B0 that came from the holding block 12-1. The data item B1 is held by the holding block 12-1 until a fourth clock pulse is output. The data item A1 is converted into a data item A2 after undergoing the second process performed by the signal processing block 13-2. The data item A2 is input to and held by the holding block 12-3 until the fourth clock pulse is output.
On the fourth clock pulse, the holding block 12-1 inputs and holds the data item D0 while outputting the data item C0 concurrently. The holding block 12-2 outputs the data item B1 while concurrently inputting a data item C1 derived by the signal processing block 13-1 from the data item C0 that came from the holding block 12-1. The data item C1 is held by the holding block 12-1 until a fifth clock pulse is output. The holding block 12-3 outputs the data item A2 while concurrently inputting a data item B2 derived by the signal processing block 13-2 from the data item B1 that came from the holding block 12-2. The data item B2 is held by the holding block 12-3 until the fifth clock pulse is output. The data item A2 is converted into a data item A3 after undergoing the third process performed by the signal processing block 13-3. The data item A3 is input to and held by the holding block 12-4 until the fifth clock pulse is output.
On the fifth and subsequent clock pulses, each of the holding blocks 12-1 through 12-4 and each of the signal processing blocks 13-1 through 13-3 repeat the operations described above. As a result, the data item A3 is output to the outside on the fifth clock pulse, a data item B3 on a sixth clock pulse, a data item C3 on a seventh clock pulse, and a data item D3 on an eighth clock pulse.
That is, when the synchronizing clock signal CLK is set for its highest frequency, the information processing apparatus 1 inputs the data item A0 on the first clock pulse, and outputs on the fifth clock pulse the data item A3 having undergone the processes performed by the signal processing blocks 13-1 through 13-3. In this case, the time required from the time one data item (one of A0, B0, C0, A0) is input to the information processing apparatus 1 until the input data item is processed and output to the outside (as one of A3, B3, C3, D3) is a time T1, as shown in FIG. 2.
Suppose now that the frequency control block 11, based on newly input frequency information Infq, sets the synchronizing clock signal CLK for half of its highest frequency (indicated in FIG. 2) and outputs the synchronizing clock signal CLK at the reduced frequency. In this case, the synchronizing clock signal CLK appears as depicted in FIG. 3, as opposed to what is shown in FIG. 2.
In the case above, the information processing apparatus 1 also operates in basically the same way as when the synchronizing clock signal CLK is set for its maximum (as indicated in FIG. 2). That is, as illustrated in FIG. 3, the information processing apparatus 1 inputs the data item A0 on the first clock pulse and outputs to the outside on the fifth clock pulse the data item A3 having undergone the processes carried out by the signal processing blocks 13-1 through 13-3.
It should be noted, however, that with the output cycle of the synchronizing clock signal CLK now doubled, it takes twice as long as the time T1 required from the time one data item (one of A0, B0, C0, D0) is input to the information processing apparatus 1 until the input data item is processed and output to the outside (as one of A3, B3, C3, D3). The time T1 (FIG. 2) at the highest clock frequency is now replaced with a time T2 which is twice as long as the time T1.
The processing time (absolute time) of the information processing apparatus 1 at the reduced frequency is twice the time it takes when the frequency is the highest. In other words, the processing performance of the information processing apparatus 1 is reduced to half of what it is when the frequency is maximized.
If the reduction in processing performance triggered by the halving of the clock frequency were kept less than half of the conventionally observed drop, by somehow raising the performance using the same clock signal, there would be power savings commensurate with the rise in the performance per unit power consumption. However, techniques for implementing such an improvement have yet to materialize.